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hal/ia32: Implement HP timer #476

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Nov 15, 2023
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9 changes: 5 additions & 4 deletions hal/armv7a/imx6ull/timer.c
Original file line number Diff line number Diff line change
Expand Up @@ -87,15 +87,16 @@ static time_t hal_timerGetCyc(void)
}


void hal_timerSetWakeup(u32 when)
void hal_timerSetWakeup(u32 waitUs)
{
spinlock_ctx_t sc;
u32 cyc;

if (!when)
++when;
if (waitUs == 0) {
++waitUs;
}

cyc = when * 66;
cyc = waitUs * 66;

hal_spinlockSet(&timer_common.lock, &sc);
*(timer_common.epit1 + epit_lr) = cyc;
Expand Down
2 changes: 1 addition & 1 deletion hal/armv7a/zynq7000/timer.c
Original file line number Diff line number Diff line change
Expand Up @@ -90,7 +90,7 @@ static time_t hal_timerGetCyc(void)
}


void hal_timerSetWakeup(u32 when)
void hal_timerSetWakeup(u32 waitUs)
{
}

Expand Down
8 changes: 4 additions & 4 deletions hal/armv7m/imxrt/timer.c
Original file line number Diff line number Diff line change
Expand Up @@ -85,17 +85,17 @@ static time_t hal_timerGetCyc(void)
}


void hal_timerSetWakeup(u32 when)
void hal_timerSetWakeup(u32 waitUs)
{
spinlock_ctx_t sc;

if (when > timer_common.interval) {
when = timer_common.interval;
if (waitUs > timer_common.interval) {
waitUs = timer_common.interval;
}

hal_spinlockSet(&timer_common.sp, &sc);
/* Modulo handled implicitly */
*(timer_common.base + gpt_ocr2) = hal_timerUs2Cyc(when) + *(timer_common.base + gpt_cnt);
*(timer_common.base + gpt_ocr2) = hal_timerUs2Cyc(waitUs) + *(timer_common.base + gpt_cnt);
*(timer_common.base + gpt_sr) |= 1 << 1;
hal_cpuDataMemoryBarrier();
hal_spinlockClear(&timer_common.sp, &sc);
Expand Down
2 changes: 1 addition & 1 deletion hal/armv7m/stm32/l4/timer.c
Original file line number Diff line number Diff line change
Expand Up @@ -192,7 +192,7 @@ void timer_setAlarm(time_t us)
}


void hal_timerSetWakeup(u32 when)
void hal_timerSetWakeup(u32 waitUs)
{
}

Expand Down
2 changes: 1 addition & 1 deletion hal/armv8m/nrf/91/timer.c
Original file line number Diff line number Diff line change
Expand Up @@ -68,7 +68,7 @@ static int timer_irqHandler(unsigned int n, cpu_context_t *ctx, void *arg)
/* Interface functions */


void hal_timerSetWakeup(u32 when)
void hal_timerSetWakeup(u32 waitUs)
{
}

Expand Down
2 changes: 2 additions & 0 deletions hal/ia32/arch/interrupts.h
Original file line number Diff line number Diff line change
Expand Up @@ -34,6 +34,8 @@
#define IOAPIC_INTPOL (1u << 13)
#define IOAPIC_DESTMOD (1u << 11)

#define LAPIC_EOI 0

/* Interrupt source override polarity flags */
#define MADT_ISO_POLAR_MASK 0x3
#define MADT_ISO_POLAR_BUS 0x0
Expand Down
26 changes: 12 additions & 14 deletions hal/ia32/cpu.c
Original file line number Diff line number Diff line change
Expand Up @@ -27,6 +27,8 @@
#include "tlb.h"
#include "init.h"

extern void hal_timerInitCore(const unsigned int id);

struct cpu_feature_t {
const char *name;
s32 eax;
Expand Down Expand Up @@ -302,7 +304,7 @@ unsigned int hal_cpuGetCount(void)
static inline unsigned int _hal_cpuGetID(void)
{
if (hal_isLapicPresent() == 1) {
return (*(volatile u32 *)(hal_config.localApicAddr + LAPIC_ID_REG)) >> 24;
return _hal_lapicRead(LAPIC_ID_REG) >> 24;
}
else {
return 0;
Expand All @@ -326,26 +328,22 @@ unsigned int hal_cpuGetID(void)
/* Sends IPI to everyone but self */
void cpu_broadcastIPI(unsigned int intr)
{
volatile u32 *p;
if (hal_isLapicPresent() == 1) {
p = hal_config.localApicAddr + LAPIC_ICR_REG_0_31;
*p = intr | 0xc4000;
while (*p & (1 << 12)) {
_hal_lapicWrite(LAPIC_ICR_REG_0_31, intr | 0xc4000);
while ((_hal_lapicRead(LAPIC_ICR_REG_0_31) & (1 << 12)) != 0) {
}
}
}


void hal_cpuSendIPI(unsigned int cpu, unsigned int intrAndFlags)
{
volatile u32 *p, *q;
if (hal_isLapicPresent() == 1) {
p = hal_config.localApicAddr + LAPIC_ICR_REG_0_31;
q = hal_config.localApicAddr + LAPIC_ICR_REG_32_63;
/* Set destination */
*q = (cpu & 0xff) << 24;
*p = intrAndFlags & 0xcdfff;
while (*p & (1 << 12)) {
/* TODO: Disable interrupts while we're writing */
_hal_lapicWrite(LAPIC_ICR_REG_32_63, (cpu & 0xff) << 24);
_hal_lapicWrite(LAPIC_ICR_REG_0_31, intrAndFlags & 0xcdfff);
while ((_hal_lapicRead(LAPIC_ICR_REG_0_31) & (1 << 12)) != 0) {
}
}
}
Expand Down Expand Up @@ -377,13 +375,11 @@ static void _cpu_gdtInsert(unsigned int idx, u32 base, u32 limit, u32 type)

void *_cpu_initCore(void)
{
volatile u32 *p;
const unsigned int id = hal_cpuGetID();
hal_cpuAtomAdd(&cpu.readyCount, 1);

if (hal_isLapicPresent() == 1) {
p = hal_config.localApicAddr + LAPIC_SPUR_IRQ_REG;
*p = (*p | 0x11ffu);
_hal_lapicWrite(LAPIC_SPUR_IRQ_REG, _hal_lapicRead(LAPIC_SPUR_IRQ_REG) | 0x11ffu);
}

hal_memset(&cpu.tss[id], 0, sizeof(tss_t));
Expand Down Expand Up @@ -420,6 +416,7 @@ void *_cpu_initCore(void)
/* clang-format on */

hal_tlbInitCore(id);
hal_timerInitCore(id);

return (void *)cpu.tss[id].esp0;
}
Expand All @@ -433,6 +430,7 @@ static void _hal_cpuInitCores(void)

/* Initialize BSP */
cpu.readyCount = 0;
_hal_timerInit(SYSTICK_INTERVAL);
_cpu_initCore();

*(u32 *)(syspage->hs.stack + VADDR_KERNEL - 4) = 0;
Expand Down
1 change: 0 additions & 1 deletion hal/ia32/hal.c
Original file line number Diff line number Diff line change
Expand Up @@ -76,7 +76,6 @@ void _hal_init(void)
_hal_interruptsInit();

_hal_cpuInit();
_hal_timerInit(SYSTICK_INTERVAL);
_hal_pciInit();

hal_common.started = 0;
Expand Down
81 changes: 81 additions & 0 deletions hal/ia32/init.c
Original file line number Diff line number Diff line change
Expand Up @@ -138,6 +138,9 @@ static int _hal_acpiInit(hal_config_t *config)
if (syspage->hs.fadt != 0) {
hal_config.fadt = _hal_configMapObjectBeforeStack(pdir, syspage->hs.fadt, syspage->hs.fadtLength, PGHD_WRITE);
}
if (syspage->hs.hpet != 0) {
hal_config.hpet = _hal_configMapObjectBeforeStack(pdir, syspage->hs.hpet, syspage->hs.hpetLength, PGHD_WRITE);
}

if (hal_config.madt != NULL) {
config->localApicAddr = _hal_configMapDevice(pdir, hal_config.madt->localApicAddr, SIZE_PAGE, PGHD_WRITE);
Expand Down Expand Up @@ -200,6 +203,83 @@ static inline void _hal_configMemoryInit(void)
}


void _hal_gasAllocDevice(const hal_gas_t *gas, hal_gasMapped_t *mgas, size_t size)
{
addr_t *pdir = (addr_t *)(VADDR_KERNEL + syspage->hs.pdir);
mgas->addressSpaceId = gas->addressSpaceId;
mgas->registerWidth = gas->registerWidth;
mgas->registerOffset = gas->registerOffset;
mgas->accessSize = gas->accessSize;

switch (gas->addressSpaceId) {
case GAS_ADDRESS_SPACE_ID_MEMORY:
mgas->address = _hal_configMapDevice(pdir, (addr_t)gas->address, size, PGHD_WRITE);
break;
default:
mgas->address = (void *)((u32)gas->address);
break;
}
}


int _hal_gasWrite32(hal_gasMapped_t *gas, u32 offset, u32 val)
{
int ret;
switch (gas->addressSpaceId) {
case GAS_ADDRESS_SPACE_ID_MEMORY:
*(volatile u32 *)(gas->address + offset) = val;
ret = 0;
break;
case GAS_ADDRESS_SPACE_ID_IOPORT:
hal_outl(gas->address + offset, val);
ret = 0;
break;
case GAS_ADDRESS_SPACE_ID_PCI:
/* TODO */
ret = 1;
break;
case GAS_ADDRESS_SPACE_ID_PCIBAR:
/* TODO */
ret = 1;
break;
default:
/* Unspecified */
ret = 1;
break;
}
return ret;
}


int _hal_gasRead32(hal_gasMapped_t *gas, u32 offset, u32 *val)
{
int ret;
switch (gas->addressSpaceId) {
case GAS_ADDRESS_SPACE_ID_MEMORY:
*val = *(volatile u32 *)(gas->address + offset);
ret = 0;
break;
case GAS_ADDRESS_SPACE_ID_IOPORT:
*val = hal_inl(gas->address + offset);
ret = 0;
break;
case GAS_ADDRESS_SPACE_ID_PCI:
/* TODO */
ret = 1;
break;
case GAS_ADDRESS_SPACE_ID_PCIBAR:
/* TODO */
ret = 1;
break;
default:
/* Unspecified */
ret = 1;
break;
}
return ret;
}


void _hal_configInit(syspage_t *s)
{
unsigned int ra, rb, rc, rd;
Expand All @@ -215,6 +295,7 @@ void _hal_configInit(syspage_t *s)
hal_config.ptable = NULL;
hal_config.madt = NULL;
hal_config.fadt = NULL;
hal_config.hpet = NULL;
hal_config.devices = MMIO_DEVICES_VIRT_ADDR;
hal_config.memMap.count = 0;

Expand Down
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