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Connectors
This connector allows for connection of expansion modules like RR-Net. Most pins are connected straight to the cartridge port, but the chip select and read/write signals are driven by the FPGA, meaning that the module must accept 3.3V logic on these pins. The pins on this connector are sometimes numbered 19 through 40 instead of 1 through 22. This numbering is given in parentheses below.
| J1 pin | Function | Cartridge port pin | FPGA pin |
|---|---|---|---|
| 1 (19) | GND | 1, 22, A, Z (GND) | |
| 2 (20) | +5V | 2, 3 (+5V) | |
| 3 (21) | INT6 | D (/NMI) | |
| 4 (22) | Spare /CS | J5 | |
| 5 (23) | RTC /CS | H4 | |
| 6 (24) | N/C | ||
| 7 (25) | /IORD | H3 | |
| 8 (26) | /IOWR | G3 | |
| 9 (27) | A5 | V (A3) | |
| 10 (28) | A4 | W (A2) | |
| 11 (29) | A3 | X (A1) | |
| 12 (30) | A2 | Y (A0) | |
| 13 (31) | D23 | 14 (D7) | |
| 14 (32) | D22 | 15 (D6) | |
| 15 (33) | D21 | 16 (D5) | |
| 16 (34) | D20 | 17 (D4) | |
| 17 (35) | D19 | 18 (D3) | |
| 18 (36) | D18 | 19 (D2) | |
| 19 (37) | D17 | 20 (D1) | |
| 20 (38) | D16 | 21 (D0) | |
| 21 (39) | GND | 1, 22, A, Z (GND) | |
| 22 (40) | /RESET | C (/RESET) |
This connector is intended for use as a debug UART, but can be used as two general GPIOs if so desired.
The pins have no ESD or short-circuit protection, but are connected straight to the FPGA. Please use caution. Signal levels are 3.3V.
| J2 Pin | Function | FPGA pin |
|---|---|---|
| 1 | GND | |
| 2 | RXD | E8 |
| 3 | TXD | D8 |
On the USB C connector, the super-speed pairs are not connected. CC1/CC2 has pull-downs to identify the port as an upstream facing port (UFP). SBU1 and SBU2 are routed to test points. VBUS can be used to power the cartridge, but no current can be sourced from the cartridge through VBUS. The connections from D+ and D- to the FPGA are protected with 20Ω resistors. D+ can be pulled up to +3.3V via a 1.5kΩ resistor.
| J3 Pin | Function | Connection |
|---|---|---|
| A1 / B1 | GND | GND |
| A2 / B2 | TX1/2+ | N/C |
| A3 / B3 | TX1/2- | N/C |
| A4 / B4 | VBUS | Diode to VSYS |
| A5 / B5 | CC1 / CC2 | 5.1kΩ pull-down |
| A6 / B6 | D+ | R5 (N6 pull-up) |
| A7 / B7 | D- | T4 |
| A8 / B8 | SBU1 / SBU2 | Test point 1/2 |
| A9 / B9 | VBUS | Diode to VSYS |
| A10 / B10 | RX2/1- | N/C |
| A11 / B11 | RX2/1+ | N/C |
| A12 / B12 | GND | GND |
The full set of Micro SDcard signals are connected to FPGA pins. Only 3.3V operation is supported.
| J4 pin | Function | FPGA pin |
|---|---|---|
| 1 | DAT2 | C11 |
| 2 | DAT3 / nCS | B11 |
| 3 | CMD / MOSI | E11 |
| 4 | +3.3V | |
| 5 | CLK / SCLK | A10 |
| 6 | GND | |
| 7 | DAT0 / MISO | C9 |
| 8 | DAT1 / nIRQ | E9 |
| Switch | Card detect | A11 |
This connector has 4 GPIO signals, +3.3V and GND. This is similar to a PMOD connector, but a 2x3 pin footprint is used instead of 1x6. The pins use odd-even numbering, as opposed to the top-bottom numbering used in a dual PMOD connector. Pin 1 is marked with a quadratic pad.
The GPIO pins have no ESD or short-circuit protection, but are connected straight to the FPGA. Please use caution. Signal levels are 3.3V on all GPIO pins.
| J5 pin | Function | FPGA pin |
|---|---|---|
| 1 | GPIO1 | B9 |
| 2 | GPIO2 | B10 |
| 3 | GPIO3 | C10 |
| 4 | GPIO4 | A9 |
| 5 | GND | |
| 6 | +3.3V |
The JTAG operates at 3.3V levels. The SRST signal causes the FPGA to reload its configuration from flash if asserted. The pinout is commonly referred to as "SWD", even though it carries the full 4-pin JTAG interface rather than just the 2-pin SWD subset.
| J6 pin | Function | FPGA pin |
|---|---|---|
| 1 | +3.3V | |
| 2 | TMS | T11 |
| 3 | GND | |
| 4 | TCK | T10 |
| 5 | GND | |
| 6 | TDO | M10 |
| 7 | GND | |
| 8 | TDI | R11 |
| 9 | GND | |
| 10 | SRST | R9 |