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FPGA IO
Marcus Comstedt edited this page Jun 12, 2022
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1 revision
- Not used
- VCCIO = 0V
- Oscillator, SDcard, GPIO
- VCCIO = 3.3V
| Pin | IO name | Function | Schematic | Litex | IO standard |
|---|---|---|---|---|---|
| E8 | PT33A | UART RXD | RXD | serial.rx | LVCMOS33 |
| D8 | PT33B | UART TXD | TXD | serial.tx | LVCMOS33 |
| C8 | PT35A | Oscillator | REF_CLK | clk48 | LVCMOS33 |
| B9 | PT38A | GPIO1 | PMOD1 | GPIO[1] | LVCMOS33 |
| C9 | PT38B | SDcard DAT0 | SD0_DAT0 | sdcard.data[0] | LVCMOS33 |
| E9 | PT40B | SDcard DAT1 | SD0_DAT1 | sdcard.data[1] | LVCMOS33 |
| A9 | PT42A | GPIO4 | PMOD4 | GPIO[4] | LVCMOS33 |
| A10 | PT42B | SDcard CLK | SD0_CLK | sdcard.clk | LVCMOS33 |
| B10 | PT44A | GPIO2 | PMOD2 | GPIO[2] | LVCMOS33 |
| C10 | PT44B | GPIO3 | PMOD3 | GPIO[3] | LVCMOS33 |
| B11 | PT49A | SDcard DAT3 | SD0_DAT3 | sdcard.data[3] | LVCMOS33 |
| C11 | PT49B | SDcard DAT2 | SD0_DAT2 | sdcard.data[2] | LVCMOS33 |
| E11 | PT51B | SDcard CMD | SD0_CMD | sdcard.cmd | LVCMOS33 |
| A11 | PT53A | SDcard CD | SD0_CD | sdcard.cd | LVCMOS33 |
- HyperRAM, Pushbutton
- VCCIO = 1.8V
| Pin | IO name | Function | Schematic | Litex | IO standard |
|---|---|---|---|---|---|
| B16 | PR2A | HRAM DQ1 | RAM_DQ1 | hyperram.dq[1] | LVCMOS18 |
| C16 | PR5A | HRAM DQ4 | RAM_DQ4 | hyperram.dq[4] | LVCMOS18 |
| C15 | PR5B | HRAM DQ2 | RAM_DQ2 | hyperram.dq[2] | LVCMOS18 |
| F14 | PR5D | HRAM RWDS | RAM_RWDS | hyperram.rwds | LVCMOS18 |
| D16 | PR8A | HRAM DQ3 | RAM_DQ3 | hyperram.dq[3] | LVCMOS18 |
| E15 | PR8B | HRAM DQ7 | RAM_DQ7 | hyperram.dq[7] | LVCMOS18 |
| F12 | PR8D | Pushbutton | USER_BUTTON | usr_btn | LVCMOS18 |
| F15 | PR11C | HRAM DQ5 | RAM_DQ5 | hyperram.dq[5] | LVCMOS18 |
| F16 | PR14A | HRAM DQ6 | RAM_DQ6 | hyperram.dq[6] | LVCMOS18 |
| G15 | PR14B | HRAM DQ0 | RAM_DQ0 | hyperram.dq[0] | LVCMOS18 |
| J13 | PR17C | HRAM /RESET | RAM_RESET# | hyperram.reset_n | LVCMOS18 |
| G16 | PR20A | HRAM PSC+ | RAM_PSC+ | hyperram.psc_p | SSTL18D_II |
| H15 | PR20B | HRAM PSC- | RAM_PSC- | ||
| K14 | PR20D | HRAM /CS | RAM_CS# | hyperram.cs_n | LVCMOS18 |
| J16 | PR23A | HRAM CK+ | RAM_CK+ | hyperram.ck_p | SSTL18D_II |
| J15 | PR23B | HRAM CK- | RAM_CK- |
- Not used
- VCCIO = 0V
- USB, Cartridge port #1
- VCCIO = 3.3V
Cartridge port D and A signals are bidirectional, where the direction and enable of the corresponding level shifters have to be controlled in accordance with the current FPGA IO direction. Other cartridge port signals are either dedicated inputs, or dedicated outputs where a high output on the FPGA pin will pull the corresponding cartridge port signal low. "c64exp" is an abbreviation for the full Litex name "c64expansionport".
| Pin | IO name | Function | Schematic | Litex | IO standard |
|---|---|---|---|---|---|
| L1 | PL26A | A0-7 enable | A_/EN_L | c64exp.a_en_n[0] | LVCMOS33 |
| L2 | PL26B | /ROML in | ROML | c64exp.roml_n | LVCMOS33 |
| M1 | PL26C | D0 in/out | D0 | c64exp.d[0] | LVCMOS33 |
| M2 | PL26D | /DMA low | DMA | c64exp.dma_out | LVCMOS33 |
| L4 | PL29C | A7 in/out | A7 | c64exp.a[7] | LVCMOS33 |
| L5 | PL29D | A0-7 dir | A_DIR_L | c64exp.a_dir[0] | LVCMOS33 |
| N1 | PL32A | D3 in/out | D3 | c64exp.d[3] | LVCMOS33 |
| P2 | PL32B | D2 in/out | D2 | c64exp.d[2] | LVCMOS33 |
| M3 | PL32D | A6 in/out | A6 | c64exp.a[6] | LVCMOS33 |
| P1 | PL35A | D5 in/out | D5 | c64exp.d[5] | LVCMOS33 |
| R1 | PL35B | D7 in/out | D7 | c64exp.d[7] | LVCMOS33 |
| N3 | PL35D | D1 in/out | D1 | c64exp.d[1] | LVCMOS33 |
| N4 | PL38A | A3 in/out | A3 | c64exp.a[3] | LVCMOS33 |
| R2 | PL38C | D6 in/out | D6 | c64exp.d[6] | LVCMOS33 |
| T2 | PL38D | D0-7 dir | D_DIR | c64exp.d_dir | LVCMOS33 |
| P4 | PL41A | A2 in/out | A2 | c64exp.a[2] | LVCMOS33 |
| R3 | PL41B | D4 in/out | D4 | c64exp.d[4] | LVCMOS33 |
| R4 | PL41C | A1 in/out | A1 | c64exp.a[1] | LVCMOS33 |
| T3 | PL41D | D0-7 enable | D_/EN | c64exp.d_en_n | LVCMOS33 |
| R5 | PL44A | USB D+ | USB_D+ | usb.d_p | LVCMOS33 |
| T4 | PL44B | USB D- | USB_D- | usb.d_n | LVCMOS33 |
| M5 | PL44C | A5 in/out | A5 | c64exp.a[5] | LVCMOS33 |
| N5 | PL44D | A4 in/out | A4 | c64exp.a[4] | LVCMOS33 |
| M6 | PL47A | A0 in/out | A0 | c64exp.a[0] | LVCMOS33 |
| N6 | PL47B | USB pull-up | USB_PULLUP | usb.pullup | LVCMOS33 |
| P6 | PL47C | Testpoint 19 | EXT_PLL+ | ||
| P5 | PL47D | Testpoint 20 | EXT_PLL- |
- Clock port, Cartridge port #2
- VCCIO = 3.3V
Cartridge port A signals are bidirectional, where the direction and enable of the corresponding level shifters have to be controlled in accordance with the current FPGA IO direction. Other cartridge port signals are either dedicated inputs, or dedicated outputs where a high output on the FPGA pin will pull the corresponding cartridge port signal low. "c64exp" is an abbreviation for the full Litex name "c64expansionport".
| Pin | IO name | Function | Schematic | Litex | IO standard |
|---|---|---|---|---|---|
| B1 | PL2A | /RESET in | RESET_IN | c64exp.reset_in_n | LVCMOS33 |
| B2 | PL2B | DOTCLK in | DOTCLK | c64exp.dotclk | LVCMOS33 |
| C3 | PL2C | /ROMH in | ROMH | c64exp.romh_n | LVCMOS33 |
| D3 | PL2D | /GAME low | GAME | c64exp.game | LVCMOS33 |
| C1 | PL5A | /RESET low | RESET_OUT | c64exp.reset_out | LVCMOS33 |
| C2 | PL5B | PHI2 in | PHI2 | c64exp.phi2 | LVCMOS33 |
| E3 | PL5C | R/W in | RW_IN | c64exp.rw_in | LVCMOS33 |
| F3 | PL5D | R/W low | RW_OUT | c64exp.rw_out_n | LVCMOS33 |
| D1 | PL8A | /EXROM low | EXROM | c64exp.exrom | LVCMOS33 |
| E2 | PL8B | A8-15 enable | A_/EN_H | c64exp.a_en_n[1] | LVCMOS33 |
| F4 | PL8C | /IRQ low | IRQ_OUT | c64exp.irq_out | LVCMOS33 |
| F5 | PL8D | /IO1 in | IO1 | c64exp.io1_n | LVCMOS33 |
| G5 | PL11A | /NMI low | NMI_OUT | c64exp.nmi_out | LVCMOS33 |
| G4 | PL11B | A9 in/out | A9 | c64exp.a[9] | LVCMOS33 |
| F2 | PL11C | A15 in/out | A15 | c64exp.a[15] | LVCMOS33 |
| E1 | PL11D | A8-15 dir | A_DIR_H | c64exp.a_dir[1] | LVCMOS33 |
| F1 | PL14A | A14 in/out | A14 | c64exp.a[14] | LVCMOS33 |
| G2 | PL14B | A13 in/out | A13 | c64exp.a[13] | LVCMOS33 |
| G3 | PL14C | C.port /IOWR | CIOWR | clockport.iowr_n | LVCMOS33 |
| H3 | PL14D | C.port /IORD | CIORD | clockport.iord_n | LVCMOS33 |
| H5 | PL17A | A8 in/out | A8 | c64exp.a[8] | LVCMOS33 |
| H4 | PL17B | C.port /RTCCS | CRTCCS | clockport.rtc_cs_n | LVCMOS33 |
| J5 | PL17D | C.port /SPARECS | CSPARECS | clockport.spare_cs_n | LVCMOS33 |
| G1 | PL20A | A12 in/out | A12 | c64exp.a[12] | LVCMOS33 |
| J1 | PL23A | A10 in/out | A10 | c64exp.a[10] | LVCMOS33 |
| J2 | PL23B | A11 in/out | A11 | c64exp.a[11] | LVCMOS33 |
| K1 | PL23C | /IO2 in | IO2 | c64exp.io2_n | LVCMOS33 |
| K2 | PL23D | BA in | BA | c64exp.ba | LVCMOS33 |
- LED, Flash, JTAG
- VCCIO = 3.3V
Note that pin N9 (CCLK) can not be mapped as a regular IO, but must be accessed through the USRMCLK special primitive. Pin R9 is connected to normal IO pin M8 to allow the FPGA to reset itself.
| Pin | IO name | Function | Schematic | Litex | IO standard |
|---|---|---|---|---|---|
| T6 | PB4A | RGB LED R | LED_R | rgb_led.r | LVCMOS33 |
| R6 | PB4B | RGB LED G | LED_G | rgb_led.g | LVCMOS33 |
| N7 | PB9A | Flash D3 | QSPI_D3 | spiflash.hold | LVCMOS33 |
| M7 | PB9B | Flash D2 | QSPI_D2 | spiflash.wp | LVCMOS33 |
| T7 | PB11A | Flash MISO | SPI_CONFIG_MISO | spiflash.miso | LVCMOS33 |
| T8 | PB11B | Flash MOSI | SPI_CONFIG_MOSI | spiflash.mosi | LVCMOS33 |
| R8 | PB13A | RGB LED B | LED_B | rgb_led.b | LVCMOS33 |
| N8 | PB15A | Flash /CS | SPI_CONFIG_SS | spiflash.cs_n | LVCMOS33 |
| M8 | PB15B | Self reset | FPGA_RESET | rst_n | LVCMOS33 |
| N9 | CCLK | Flash SCLK | SPI_CONFIG_SCK | ||
| R9 | PROGRAMN | Reset in | FPGA_RESET | ||
| T10 | TCK | JTAG TCK | JTAG_TCK | ||
| R11 | TDI | JTAG TDI | JTAG_TDI | ||
| T11 | TMS | JTAG TMS | JTAG_TMS | ||
| M10 | TDO | JTAG TDO | JTAG_TDO |